Shilpa Reddy Krishna Reddy
Amstelveen
Summary
Ambitious Electrical Engineer with record of continuously exceeding both company and personal goals. Expertise includes Cadence Virtuoso for circuit design and Mixed Signal Verification. Extensive knowledge of electrical engineering design and applications. Eager to contribute to team success through hard work, attention to detail and excellent organizational skills.
Overview
9
9
years of professional experience
Work History
ANALOG DESIGN ENGINEER
Intel Corp.
01.2020 - Current
- Involved with design and analysis for the Temperature and Humidity Sensors for industrial & automotive parts
- Involved in design and verification on blocks like ADC, IO, amplifier, LDO, oscillators, bandgap and power management circuits
- Involved in top level AMS verification ESD checks and layout best practices for circuit design.
PRODUCT ENGINEERING INTERN
Analog Devices, Inc.
07.2019 - 09.2019
- Involved with Technology & Manufacturing Group (TMG) failure analysis cycle for business units across Maxim
- Circuit design and layout debug analysis using Cadence for PLL, ADC and RF based circuits in multiple nodes.
ANALOG DESIGN ENGINEER
Intel Corp.
07.2016 - 08.2018
- Involved in analog design cycle of high voltage automotive and industrial gate-drivers for Brushed, brushless and stepper motors for clients on global scale
- Designed bandgap, charge-pumps, oscillators, pre-drivers, IO’s, LDO, Class AB op-amps, pre-drivers & bias generation IPs for Release to Market of 4 gate drivers
- Presented a paper on “LVDS TX Architecture with better CMFB Stability and Area Reduction” at TIITC 2017
- Filed a patent disclosure on “Improved common mode feedback differential amplifier architecture”
- Involved in analog top-level design verification, layout floorplan of individual IP’s, ESD checks at chip level.
Analog IC Design Intern
INTEGRATED CIRCUIT (IC) DESIGN INTERN, Texas Instruments, Inc
07.2015 - 06.2016
- Design of process compensated Drive Strength Programmable CMOS I/O Buffer aimed at reducing 40% spread of output impedance across processes, temperature and voltage variations (Analog Technology Development-High Performance Analog Team)
- Design of sub-components for an IO test-chip with LVDS multiplexed with GPIO and FET based ESD failsafe structure for low power & high performance 65nm technology (MCU IO and Standard Cell Library Team)
- Design of 3 voltage level SRAM stacking implementation with variable voltage levelled level up and level down Level Shifters along with buffer mode using control signals (Project under KILBY LABS).
Education
M.S - ELECTRICAL CIRCUITS & SYSTEMS
UNIVERSITY oF CALIFORNIA SAN DIEGO
San Diego, CA12.2019
B.E( Hons.) & Msc(Hons.) - B.E. in Electrical & Electronics + MSc. Physics
BITS PILANI
Pilani, INDIA06.2016
Skills
- Cadence Virtuoso
- HSPICE
- MATLAB
- Verilog
- LTSPICE
- Simulink
- AutoCAD
- Proteus
- VHDL
- C
- Circuit Design
- MATLAB
- Processes
- Verilog
- VHDL
- System-level electrical design and integration
- Problem resolution
- Design process tool methodology
- Semiconductor process system
Accomplishments
DESIGN OF DIRECT CONVERSION RECEIVER AT 2.15GHZ(APRIL 2019-JUNE 2019)
-Consisting of noise cancelling R feedback LNA, current mode passive mixer, op-amp based TIA and LO divider at 25% duty cycle
-Achieved a Noise Figure (DSB) of 2.5dB and a current consumption of 10mA at 30dB gain & 1MHz BW in 180nm node
DESIGN OF LOW POWER TEMPERATURE SENSOR FOR BIOMEDICAL APPLICATIONS(SEPTEMBER 2018-DECEMBER 2018)
-Low power senor at 0.8V employing resistive frequency locked oscillator implementation and digital counter in 180nm node
-Coefficient of correlation post linear regression was R=0.8945
DESIGN OF DIGITAL CIRCUITS USING CNT(CARBON NANOTUBE) FETS(AUGUST 2014-MAY 2015)
- Designed 4,8,12 and 16bit multipliers using HSpice and sized DG, DOMINO and TSPC topologies for CNTFET multipliers
-Compared and analyzed the sizing of circuits using CMOS and CNTFET topologies for optimum Power Delay Product
- Presented a Review Paper on CNTFET Ternary Circuits in APOGEE 2015 (Annual Technical Festival, BITS Pilani)
Timeline
ANALOG DESIGN ENGINEER
Intel Corp.
01.2020 - Current
PRODUCT ENGINEERING INTERN
Analog Devices, Inc.
07.2019 - 09.2019
ANALOG DESIGN ENGINEER
Intel Corp.
07.2016 - 08.2018
Analog IC Design Intern
INTEGRATED CIRCUIT (IC) DESIGN INTERN, Texas Instruments, Inc
07.2015 - 06.2016
M.S - ELECTRICAL CIRCUITS & SYSTEMS
UNIVERSITY oF CALIFORNIA SAN DIEGO
B.E( Hons.) & Msc(Hons.) - B.E. in Electrical & Electronics + MSc. Physics
BITS PILANI
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