Navya Sree Anumula
FPGA Designer
Amstelveen
Summary
Dynamic professional knowledgeable in Satellite Digital Electronic Systems. Effective problem solver at ISRO for about 6 years in the field of Design, Reliability Analysis and Testing for Satellite Launches
Overview
8
8
years of professional experience
4
4
years of post-secondary education
Work History
FPGA Design Engineer
AimValley
12.2022 - Current
- Designed and validated substitution of outdated EXAR chip, employed in single-channel T1/E1 clock recovery circuit with T1/E1 framer
- Design Activities: Handling design across Clock domains, FSM design, Library aware RTL coding, Setting Design Constraints, Logic Synthesis, Place n Route, Static Timing Analysis, FPGA Prototyping, Design Validation.
- Identified bottlenecks in existing systems, proposing innovative solutions to improve overall performance.
- Verification of 1G-10G Smart Small Form-factor Pluggable (SFP) for in-band data control link capabilities and handling various tagging/ encapsulation techniques in Ethernet packets
- Developed Python scripts to evaluate jitter performance of Phase-Locked Loop (PLL) and Synchronous Ethernet (SyncE) functionality SFP transceivers
Control Systems Design Engineer
URSC, ISRO
07.2019 - 07.2022
- Part of team designing Navigation & Guidance and Motor Drive Electronics for Chandrayaan-3 Lander
- Carried out FPGA design for Antenna Drive Electronics based on micro step drive
- Part of team to evaluate Risk for Human Missions using Probability Risk Assessment models
- ISO 9001-2015 activities representative for division of 5 teams with 20 team members
- Carried out End to End Failure Mode Effect Analysis for multiple projects
- Developed Python scripts for the assessment of tele-command telemetry data utilizing a logic analyzer
- Optimized circuit complexity and reliability based on expected stress conditions and life expectancy of subsystems
- Awarded Highest Rating for 2020 during performance evaluations
- Project Manager (Product Assurance – Electrical) for XPoSat mission comprising 5 teams of 20 team members
Test and Evaluation Engineer
URSC, ISRO
07.2016 - 06.2019
- Responsible for Circuit Analysis, Test Planning, Integration Testing, Simulation testing, Reliability Analysis, Stress Analysis and Pre launch Appraisals for Satellite Control and Drive Electronics
- Created 10+ test plans for 5 Electronic subsystems (Navigation & Guidance, Onboard computer, Attitude and Orbit Control, Motor Driver Electronics, Telemetry and Tele command)
- Zero failure rates reported in subsystems for ~20 satellite launch projects
- Automated Test Analysis using python script : 6% man days efficiency gains per quarter
- Did design Reliability Analysis on Electronics Systems to enable third party consultancies underwrite insurance premiums for projects
- Part of FPGA verification Team used in Drive Electronics of Satellite
- Completed 20+ Non-conformance management in Digital Electronics subsystems across various spacecrafts
- Completed Pre-Launch Appraisals for Control Subsystems for Satellite launches used for Launch Acceptance
Education
Bachelor of Technology - Avionics
Indian Institute of Space Science And Technology
Kerala, India 08.2012 - 05.2016
Skills
VHDL & Verilog
Scripting Languages (Python, bash)
FPGA and ASIC Design
Digital Circuit Design
Proficiency in ModelSim, Quartus, Vivado
Timeline
FPGA Design Engineer
AimValley
12.2022 - Current
Control Systems Design Engineer
URSC, ISRO
07.2019 - 07.2022
Test and Evaluation Engineer
URSC, ISRO
07.2016 - 06.2019
Bachelor of Technology - Avionics
Indian Institute of Space Science And Technology
08.2012 - 05.2016
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