Summary
Overview
Work History
Education
Skills
Languages
Details
Timeline
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Naim Far

Naim Far

Nazareth

Summary

Dynamic Senior Verification Engineer with 25 years of extensive experience driving innovative solutions in digital test engineering and verification environments. Expertise includes leading technical teams, developing robust verification frameworks, and ensuring high-quality deliverables across complex projects. Strong background in integrating advanced debug capabilities and migrating proprietary tools to industry standards. Comprehensive understanding of the full pre- and post-silicon development cycle cultivated through significant roles at industry leaders such as Samsung, Intel, Qualcomm, Zoran and Marvell. Passionate about Leading and advancing verification teamwork and methodologies and promoting best practices, with exceptional multitasking abilities and communication skills that facilitate seamless collaboration across teams to enhance project execution.

Overview

26
26
years of professional experience

Work History

Senior Verification Engineer

Samsung Semiconductors
02.2025 - Current
  • Led verification of digital-to-analog interfaces for mobile camera sensors at Samsung Semiconductors.
  • Developed and enhanced UVM-based verification agents for analog behavior emulation.
  • Validated analog-to-digital interface functionality through rigorous testing protocols.
  • Collaborated with cross-functional teams to ensure high-quality project deliverables.
  • Integrated advanced debug capabilities to streamline verification processes.

Technical Lead Production Digital Test Engineer

Intel
04.2016 - Current
  • Technical Leader in the team that is responsible for the HVM reset flows, and the infrastructure of the Tester’s patterns generation.
  • My work includes enabling the reset on SoC emulation models, and partly on simulation models, with lots of integrational debug.
  • Once silicon is ready, I am responsible for the Power-On activity on silicon, up until all resets are passing on silicon.
  • I am responsible for the (Intel Proprietary) infrastructure/tool for Testers Patterns generation, used by the content teams, who build their patterns upon our reset, using the tools, that are python based.
  • Other position that I took up on myself, beyond my part in the team:
  • Maintenance and development of Test-Program debug tool on the Tester, supporting all Israel manufacturing department Digital Engineering activities.
  • Leading intel’s new debug capabilities, to become lead chip producer and enabler.
  • Migrate and maintain code repo to gitlab.
  • Migrating from “Intel Proprietary Formats” to “Industry Standard formats (ICL/PDL/STIL)” and developing new tooling that support them.
  • Defining how future Intel HVM resets should look.

Senior Verification Engineer

Intel
08.2014 - 04.2016
  • Writing from scratch and maintaining verification environment of a few blocks in the Computer Vision Engine.
  • As a verification Engineer, I was responsible for the Environments, the flows, the coverage and the debug.
  • I also worked with Certitude to validate the Verification Environment and stimuli are really catching bugs.
  • The Environment was written in OVM, the RTL was in SystemC.

Lead Verification Engineer

Qualcomm
08.2011 - 08.2014
  • Lead of the verification team working on a central Bus-Access-Module (BAM).
  • A DMA Module used by many peripheral IPs, to automate handling the Memory Bus accesses of the peripherals.
  • Needing to maintain 2 separate environments; the legacy verification stand-alone environment written in Vera (Synopsys), and the System Verilog environment (UVM) supplied for clients to handle their integrated BAM.
  • I was responsible for the costumers’ support, technical work, and leading 2 verification engineers in my team.
  • As part of the verification work, we used Certitude and Jasper for formal verification.
  • I also built verification environments for 2 small blocks, from scratch, in System Verilog, to learn System Verilog (OVM), I also built a tool that converted OVM to UVM.

Verification Engineer

Zoran Microelectronics
04.2007 - 08.2011
  • Verification Engineer working in the Video team, Camera On A Chip department, working with Specman/ERM.
  • Responsible for the whole Video pipe, and few sub- blocks.
  • I also wrote few SAE verification environments in Specman, including reference models.
  • In other task, I wrote the TLM Interface between Specman and SystemC, while another engineer wrote the reference model in SystemC.

Verification Engineer

Marvell
02.2002 - 04.2007
  • In my 5 years of work in Marvell, I did various types of tasks in the verification team.
  • Starting from writing BFMs, reference model of the ARM Memory Sub System, and general verification tasks:
  • BFM: Written in C++ and using PLI Interface to communicate with RTL.
  • The Top level was written in Verilog, and the stimulus in Perl Based language called HLVL.
  • I wrote most BFMs, and supported many teams that used my BFMs.
  • ARM Memory SubSystem Reference Model: Written in C++, and includes Cache, TLB , L2 Cache and MMU.

System Architecture Student

IC4IC
01.2001 - 01.2002
  • Throughout my work in IC4IC I did the following tasks:
  • Spec of ATM-UMI unit (ATM multiplexing)
  • Wrote MicroCode for different engines in the chip
  • Submitted 2 patents.

Software Validation Student

Mellanox
01.2000 - 01.2001
  • Throughout my work in Mellanox I did the following tasks:
  • Distributed application that transfers packets between different hosts that run the application, using Threads and sockets.
  • Tcl-Tk application that showed the router and its ports. The details of the ports and their registers
  • Post silicon tests writing to test accessibility of all registers in the chip.

Education

B.sc - Computer Science

Technion Haifa
Israel

Skills

  • UVM and System Verilog
  • High experience in various HW development tools, sa simvision, indago, vcs, questa, Verdi, Jasper
  • scripting: python, cshell, perl and tcl
  • Fast Learner
  • Independent and motivated
  • High communication skills in 3 languages: 1 English 2 Hebrew 3 Arabic
  • Multitasking: ability to do multiple tasks in parallel, such as development and multiple supporting tasks
  • Excellent Team work and collaboration
  • Coverage-driven verification
  • Emulation platforms
  • SoC verification
  • Constraint random testing
  • Assertion-based verification (SVA)

Languages

Arabic
Hebrew
English

Details

  • Phone Number: 0542316580
  • Naim.far@gmail.com
  • Links
  • Https://www.linkedin.com/in/naim-far

Timeline

Senior Verification Engineer

Samsung Semiconductors
02.2025 - Current

Technical Lead Production Digital Test Engineer

Intel
04.2016 - Current

Senior Verification Engineer

Intel
08.2014 - 04.2016

Lead Verification Engineer

Qualcomm
08.2011 - 08.2014

Verification Engineer

Zoran Microelectronics
04.2007 - 08.2011

Verification Engineer

Marvell
02.2002 - 04.2007

System Architecture Student

IC4IC
01.2001 - 01.2002

Software Validation Student

Mellanox
01.2000 - 01.2001

B.sc - Computer Science

Technion Haifa

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Naim Far